The present invention relates to a coded-modulation system, in particular, relates to a Trellis-coded modulation system which maps a coded signal considering both the error in radio space and the error correction capability.
A prior Trellis-coded modulation system is described in "Trellis-coded modulation with redundant signal sets" by G.Ungerboeck, IEEE Com. Mag. February 1987, pp 5-21, in which a convolution coding circuit for error correction adds n number of redundant bits to m number of input bits, and (m+n) number of output bits are modulated in a 2.sup.m+n levels multi-level modulator.
FIG. 1 shows a block diagram of a prior Trellis-coded modulation circuit, in which FIG. 1A is a transmit side, and FIG. 1B is a receive side. In the figure, the numeral 2 is an encoder, 3 is a mapping circuit, 4 is a modulator, 5 is a demodulator, 6 is a decoder, and 10 is a clock recovery circuit.
In a Trellis-coded modulation system, an input signal is encoded for each symbol so that Euclid length between symbols is the maximum on a signal space with the combination of an error correction technique and a modulation-demodulation technique. The Trellis-coded modulation system provides the higher coding gain than a prior error correction system which encodes each symbol so that the Hamming length between symbols is the maximum.
In FIGS. 1A and 1B, an input digital signal is applied to the encoder 2 which is a convolutional encoder for error correction, and adds some redundant bits to the input digital signals. The output of the encoder 2 is applied to the mapping circuit 3 which relocates each symbol through Set-Partition. The encoder 2 and the mapping circuit 3 operate with the common clock rate. The output of the mapping circuit is transmitted through the modulator 4. On a receive side, the received signal is demodulated by the demodulator 5 the output of which is applied to the decoder 6, which effects the error correction for the error correction code encoded by the encoder 2. The output of the decoder 6 is an output digital signal. The decoder 6 operates with the clock signal of m bit/T rate by the clock recovery circuit 10 which recovers the clock signal at the output of the demodulator 5. It should be noted in FIGS. 1A and 1B that the circuits, including the encoder 2, the mapping circuit 3, the demodulator 5 and the decoder 6 operate with the common clock signal of the clock rate m bit/T, where m is an integer larger than 2, and T is a period of each symbol.
However, a prior Trellis-Coded modulation system has the disadvantage that the improvement of the coding gain is not enough as described below.
When m=4 (which means that an input signal has 4 ( - bits), and n=1 (which means that a single redundant bit is added), the number of levels increases from 16QAM to 32QAM as shown in FIG. 2, in which each dot shows a symbol, the length between the center O and each dot shows the amplitude of the symbol, and the angle between the horizontal line and the line between the center O and the symbol shows the phase of the symbol. It should be appreciated in FIG. 2 that the length between symbols in 32QAM signal is about half of that of 16QAM signal when the mean power of 16QAM signal is the same as that of 32QAM signal.
The decrease of the symbol spacing deteriorates the necessary C/N (carrier to noise ratio) for providing the predetermined error rate. Therefore, the decrease of the symbol spacing deteriorates the coding gain considerably.
Further, the increase of the levels in the Trellis-coding modulation system demands the more accurate operation of a modulator and a demodulator since less error in amplitude and phase of a QAM signal is allowed.